In order to verify logic design formally, the model checking approach based on propositional Chaussures Louis Vuitton Homme Pas Cher temporal logics has been proposed and the approach has been successfully applied to verify finite state machines. Although many temporal logics have been exploited as specification languages, some of them do not have enough expressive power to characterize arbitrary behavior of finite state machines, while others have difficulties in finding design errors. Considering these problems, one of the authors proposed regular temporal logic (RTL). RTL is expressively equivalent to the class of regular sets, and it has a simple algorithm for finding errors. RTL cannot describe, however, a property called fairness, which is defined over infinite sequences, because it is defined over finite sequences. In this paper, firstly, we introduce a new temporal logic infinitary regular temporal logic (∞RTL), which is able to describe fairness, and show that its expressive power is equivalent to the class of finite unions of regular sets and ω-regular sets. Secondly, we show how to reduce the formal verification of finite state machines to the model checking Ceintures Louis Vuitton problem of ∞RTL and we prove that Louis Vuitton Damier Azur the complexity of the model checking problem is nonelementary.

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